The Second International Forum on Next Generation Multicore/Manycore Technologies

Welcome to IFMT'10

Welcome to the Second International Forum on Next-Generation Multicore/Manycore Technologies IFMT’10.

This year the forum is affiliated with ISCA'37, and will be held on Saturday June 19th, 2010,  in Saint-Malo, France.

In cooperation with the ACM


 

Call for Papers

With the tremendous advances in process technology and the non-scalability of complex monolithic designs, multicore architecture is becoming the design of choice for high-end machines to embedded devices. The number of cores per chip is expected to grow, even to double, every two years. Although these advances are providing us with a lot of opportunities, they are also giving us a lot of design challenges, such as bandwidth requirement, power (both static and dynamic) and reliability, memory wall, parallelization, etc.

One particularly important focus area is power issue. With the process technologies going below 22 nm, in the very next years, we will not be able to exploit all available transistors because of the excessively increasing power dissipation. Aggressive techniques of power gating (by turning off parts of the chip for example) will be necessary to make the chip usable, especially when the application is not embarrassingly parallel. Furthermore the chip will be subject to soft errors, reliability and aging issues that require us to think of innovative architectural, system level  and programming model solutions to these problems.

This forum aims to provide an avenue to foster communication among academia and industry in all aspects of next-generation multicore technologies, especially those related to architectural features to support multicore programming and operating systems. Authors are invited to submit papers representing their original work in (but not limited to) the following topics targeting architectural support for multicore/manycore systems:

  • Support for parallel programming models
  • Performance modeling and analysis
  • Support for thread management and thread-level speculation
  • Cache hierarchy design
  • Interconnection and network on chip
  • Power dissipation
  • Reliability issues
  • Simulation tools
  • Homogeneous and heterogeneous architecture
  • Security issues
  • Multicore support for Virtualisation

Papers should be 12 pages or less in length, using the ACM Word or Latex style templates. Papers should describe original work not published elsewhere. Proceedings will be published in ACM International Conference Proceedings Series (AICPS), and will be on the ACM Digital Library. Papers are to be in PDF format.

 

 

Important Dates

Paper Submission Deadline:  9 April, 2010 11:59pm CET
Deadline extended to 16 April, 2010 11:59pm CET

New Firm Deadline 20 April, 2010 11:59pm CET

Notification of Acceptance/Rejection: 4 May, 2010
Camera-ready copy due: 14 17 May, 2010

Last Updated on Wednesday, 12 May 2010 20:20